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Cadence

Principal/Lead Verification Engineer (数字前端验证) - IP Group

收藏职位
  • 我要分享
  • 32万-55万/年
  • 上海
  • |
  • 3年以上
  • |
  • 本科
  • |
  • 全职

职位诱惑: 年终奖金,五险一金,福利好,股票期权

发布时间: 2019-07-19发布

职位描述

Position Description:
1.Deliver/implement advanced verification solutions by utilizing Cadence’s Incisive Verification product portfolio. The engineer should be able to act as a strong team member and contributor, leading team projects and initiatives. Exercise judgment within generally defined practices and policies.
Specific duties include:
1.Deep understanding on ASIC design and verification flow
2.Excellent knowledge of advanced verification methodology like eRM/OVM/UVM/VMM
3.Familiar with Cadence’s Incisive Plan to Closure Methodology (IPCM)
4.Proficiency in System Verilog, System C and/or e (Specman)
5.Developing and using Verification Components (eVC,OVC,UVC,VIP)
6.Developing and using assertion based verification and formal analysis methods
7.Skilled in scripting language, such as Perl,C shell,Python,Makefile
8.Assessing the project verification requirements
 
Position Requirements:
Essential Qualifications:
1.BS degree with 4+ years of applicable experience, MS degree with 2+ years of applicable experience in electrical engineering, microelectronics, comparable engineering science or solid state physics. 
2.Essential that the individual demonstrates strong communication, verbal and written. Requires good communication skills in English.
 
Desirable Qualifications:
1.Will have demonstrated hands-on experience and expertise with Cadence verification design tools or equivalent tools, flows and methodologies required to execute a verification project.
2.Will have demonstrated successful completion of 3+ verification projects as an individual contributor
3.Will have DDR project verification experience

职位发布者

cadence hr

Sr.Manager&BP

7天

简历处理用时

90%

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